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| Car navigation system hardware circuit |
| 2015/10/19 |
Digital signal processors DSP with high-speed operation and data processing function, with its high performance and low power consumption advantages for real-time navigation system mathematical calculation provides an efficient hardware platform. In modern weapons and equipment, design of vehicle navigation system based on DSP chip, it plays an important role in the fields of both civilian and military, the system has high reliability, security, etc. 1 working principle of the vehicle navigation system Vehicle navigation system's main function is coded orthogonal signal timing acquisition gyroscope, accelerometer and odometer input signal input, and handle the collected data are necessary, in order to realize the navigation solution. At the same time will collect data through RS422 bus and CAN bus to ground monitoring equipment; And through RS422 bus receive related commands and parameters. The system structure is shown in figure 1. 2 the system hardware design 2.1 design of the processor and memory Vehicle navigation system circuit adopts TMS320C6713B - A200 as DSP of TI company, the DSP chip nominal frequency is 200 MHz, working at 160 MHz DSP processing capacity of 1600 MI, s - 200 mflops 1/1. Crystal up 40 MHz to the use of the DSP of the clock input, after internal phase-locked loop frequency doubling as a clock, DSP work using a TPS70345 voltage regulator with IO voltage of 3.3 V and 1.2 V voltage of the kernel; With a capacity of 16 MB MT48LC4M3282TG - 7 it as a SDRAM memory chips, direct access to the DSP EMIF bus, memory SDRAM chip address line BA1, BA0 and A11 ~ A0 DSP chip EA15 ~ EA2, cable D31 ED31 ~ ED0 ~ do. FlashRom chip address line A22 ~ A0 GP13 ~ CP11 DSP chips and EA21 ~ EA2, cable DQ15 ~ DQ0, after ED15 ~ ED0, initialization time GP13 ~ GP13 pin status to high, SDRAM chips selected signal by DSP chip of CEO; With a capacity of 16 MB S29GL128N10TFIR1 chip for FlashRom memory, FlashRom chips selected signal by DSP chip CE1. The DSP chip of CE1 received FlashRom elected, is to use from ROM loading because of the guide way, the BOOT program in FlashRom memory. Read and write memory signals are received on the AWE signal of DSP chip. Through DSP EMIF bus interface to access external storage, can be controlled by manipulating the register external memory access, simplify the design of the circuit. 2.2 the power supply design Input power for 27 + 9 V car navigation system, the MHF + 28515 converts 24 V to + 15 V and + 5 V voltage, MHF + 28515 to 16 ~ 48 V input voltage range, output power 15 W, the + 5 V voltage output maximum power is 7.5 W, current 500 mA, + 15 V voltage output maximum 5 W, respectively, circuit 330 mA. The vehicle navigation system itself + 5 V power supply circuit using the current is about 1000 mA, so provides a + 5 V, current 140 mA > output for external use, to meet the requirements of system of the various components of the power supply, power supply system design for vehicle navigation system. MHF + 28515 output of + 5 V power supply for the whole module provides digital power supply, the CAN bus protocol chip part such as the chip directly using the power supply + 5 V work; Other circuits using the converted power supply its treatment methods include: through TPS70345 voltage regulator to convert + 5 V power supply to 3.3 V and 1.2 V power supply, 3.3 V for DSP peripheral circuit and SDRAM, Flash chips use, such as 1.2 V for the use of DSP kernel; Through TPS70351 voltage regulator to convert + 5 V power supply to 3.3 V and 1.8 V voltage, 3.3 V for the use of FPGA peripheral circuit, optical coupling, chips, 1.8 V for the use of FPGA kernel; Through two DC/DC module NKE0503 converts + 5 V power supply voltage of 3.3 V, a RS422 MAX3490 of isolating circuit and optical coupling is used, another for the use of RS232 MAX3232 of isolating circuit and optical coupling. Through a DC/DC module NME0505 isolation, + 5 V power supply for MAX481, CAN bus transceiver and its light coupling channel is used. Output MHF + 28515 + 15 V power supply for the whole module provides simulation power supply, the + 15 V voltage by three-terminal voltage regulator JW78M05 converts voltage + 5 V analog voltage, for the use of LM3940IMP and REF196; + 5 V analog voltage by LM3940IMP converted into analog voltage of 3.3 V for the op-amp supply; + 5 V analog voltage by REF196 converted into analog voltage of 3.3 V for bridge power supply; + 15 V and 15 V voltage is for op-amp OP497 power supply. 2.3 the input signal Vehicle navigation system circuit input signal three accelerometer signal, 3 road gyro signal, two odometer signals, two signposts frequency signal, a driving state signal, 9 state detection signal and 10 road temperature measuring signal. The signal form of accelerometer signal is a reversible pulse, amplitude TTL, full scale for 256 kHz, 16-bit counter count of 3 road, rising along the trigger, interrupt five latches, accelerometer signal using RC filter and belt Schmitt trigger input reverser for plastic processing, and then through the 74 lvc244 level after transformation is introduced into the FPGA. The signal form of gyro signal is a coded orthogonal signal, amplitude high level 4 ~ 5 V, low level 0 ~ 0.8 V, current 8 mA, or less frequency 1.5 MHz, or less phase difference of 90 ° plus or minus 20 °, 16-bit counter count of 3 road, rising along the trigger, interrupt five latches, gyro signal is the same as the accelerometer signal, plastic processing. And standard frequency signal frequency is 128 kHz, amplitude, TTL signals need to be plastic. Therefore, the frequency signal processing form is the same as the accelerometer signal processing method. Odometer signals including two road odometer, odometer driving state signals and 1 road 1, 12 V amplitude, driving ability 30 mA, optical coupling isolation, set up two 16-bit counter and a status register, record the odometer and status information input pulses, odometer rising along the trigger pulse count, interrupt latch; Demand driving State signal State available commands enabled and prohibited, enabling State when the State = 1, odometer signal addition count; When the State = 0, subtraction count; Odometer prohibited state signal addition count, odometer signal by RC filter circuit and protection of diode, then the light into the FPGA. State detection signal including 3 signal detecting module, 3 road high pressure signal and 3 machine shake state signals, the signal form of switch quantity, amplitude of TTL, machine shake state signals and high pressure to optical coupling isolation. Moding detection signal processing form and parameter selection is the same with the accelerometer signal; High pressure signal and the machine detection signal processing form and gyro signal. Temperature measuring signal including 10 temperature resistance input and 1 road temperature resistance public input, in - 45 ~ + 70 ℃ temperature range, temperature resistance and module of three high precision resistance bridge, according to the working principle of the bridge, the bridge arm resistance value should be less than the minimum value of temperature resistance, and should consider certain redundancy, temperature coefficient calculating formula for R0 x 3.85 x 10-3, including R0 is 0 ℃ resistance, with high precision resistor and 12 of the AD, A/D converters > 0.5 ℃, the available way switch to achieve more. Bridge two arms midpoint respectively access with operational amplifier, and then through stage amplifier after picked by A/D conversion chip temperature test results, A/D conversion chip serial interface chip, and DSP McBSP1 interface connection, the chip resolution for 12, and have 10 mu s conversion time and maximum no.11 A/D input. In the vehicle navigation system circuit design adopted in the design of CAN bus. CAN bus controller adopts SJA1000T independently, using 16 MHz crystal to cheer for the clock input, through the software configuration ID and data transmission baud rate, maximum rate is 1 Mbit s. - 1. The bus controller using data address reuse, the FPGA converted to DSPEMIF bus connection. CAN bus controller using TTL level signal (5 V), and the signal of 3.3 V level between the FPGA in the need to use SN74LVC4245 level transformation. CAN bus receiver using Philips Semiconductors company PCA82C250. The bus controller and data transmission between transceiver signal with optical coupling isolation. 2.4 the FPGA design The on-board navigation system circuit adopts FPGA processing module control logic, the count of each input signal and serial interface communication protocol. The FPGA to count of input signal, and the standard frequency signals frequency division to occur 5, the interrupt 5 signals at the same time latches on the counter value. DSP can access the FPGA's internal resources, through the EMIF bus address space occupied EMIF bus CE2. FPGA loading Mode to Master Serial Mode (Master Serial Mode), the FPGA function block diagram is shown in figure 3. The FPGA design including the design of the accelerometer signal counter, counter design, odometer gyro signal counter design, gyro frequency, standard frequency divider design, state detection and fault detection signal and the serial communication interface design. Accelerometer input is reversible pulse signal, each channel accelerometer input signals including 3 road, + A, -a &gnd, according to the design requirements, + A signal on the pulse count value increases, - A signal with pulse count value decreased, when when marking points frequency interrupt occurs, will count results in the latch. The 16-bit counter in the FPGA design, power on reset counter to 0, + A signal on the pulse count when add 1, - A signal with pulse count value minus 1, when marking points frequency interrupt occurs, will count results in the latch, DSP can be accessed through the EMIF latch accelerometer signal counter results. Gyro signal input form for orthogonal coded signal, each channel gyro signal input signal including 3 road, is A, B and DGND respectively, when A former XiangChao B phase 90 ° count value increase, when A phase lag B phase 90 ° count value decreases. When designing the input signal through the phase detecting circuit, identify A and B road signal phase successively, and produce two lines of four times the frequency of the reversible pulse signal, then the reversible pulse count, when the frequency signal interrupt occurs, the counting result in the latch. Odometer signs include two road counting input and driving state all the input signal, counting input using a 16 bit counter each road, when an interrupt occurs will counter value in the latch; Traffic STATE signals (STATE) to electricity initiative for invalid STATE, the user through the command sets the STATE status is valid. The STATE signals are in a valid STATE, the STATE is 1, odometer counter incrementing counter; If the STATE of 0, the odometer counter countdown; And when the STATE signals are in a STATE of invalid, odometer counter increasing count. On the 16-bit counter is designed in the FPGA, the electric reset the counter to 0, the value of the counter are increased, and the counter plus 1, when marking points frequency interrupt occurs, will count results in the latch. DSP can be accessed through the EMIF latch to get the result of the gyro and frequency counter. Standard frequency divider is used to standard frequency signal frequency division, have latched inside the FPGA acceleration counter, gyroscope and odometer counter count value and state of the state of the interrupt signal detection signal. In FPGA won the bid by a predetermined frequency divider of the device and a counter, dividing can be set by software programming and DSP to write need to reserve the device through the EMIF bus frequency division of the number, the number of frequency pulse counter records, count to counter output as fixed values and reset, and counter output to DSP interruption, and latches within the FPGA acceleration counter, gyroscope and odometer counter count value and state detection signal. State testing signals for the switch quantity, in an address, a representative each state all the way. In FPGA to design a 16-bit registers, storing driving state, state of high voltage signal, machine shake detection signal status and moding detection signal status, and when the interrupt signal by latches latch. Fault detection signal is through a vector address write fault detection, according to the fault detection vector each concrete is 0 or 1, by the programmable logic devices set automatic fault detection vector output pin. Set an 8 bits of storage in the FPGA, used for storage of fault detection vector, after driving the output signal. Inside the FPGA design the serial protocol module, RS232 and RS422 serial interface via an external circuit. Integrated protocol chip reference ST16C2552 to carry on the design, the MODEM control were cut. The serial interface baud rate also can be set. 
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